Panda, Abhipsa (2012) VLSI Implementation of a Demand mode Dual Chamber Rate Responsive Cardiac Pacemaker. BTech thesis.
This project is aimed to design a dual chamber rate responsive cardiac pacemaker, implement it in VLSI and improvise on it for real time safety critical
A state machine approach has been followed to achieve the desired purpose. The heart of the pacemaker system rests in the pulse generator which forms the major portion of the project. It has been developed using VHDL and implemented in hardware using FPGA. In the FSM, first an input event is detected. Once this input is detected a timer is set for approximately 0.8 sec, which will be the time between heartbeats, thus giving us 72 heartbeats per minute. Once the timer expires we check to see if a new event is detected. If one is detected we repeat the process of detection and waiting. If one has not been received we need to stimulate the heart and then repeat the process of
detection and waiting.
The code has been optimized and modified for different pacemaker modes.Adequate effort has been put in for designing a sensing circuit and other peripherals like memory, data compression techniques and remote monitoring equipment,culminating in suggestions for improvement in respective areas. It closes with pacemaker testing for real life applications and scope for further work in the field.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||VHDL, pacemaker, pulse generator, rate responsive, FPGA implementation.|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Ms. Abhipsa Panda|
|Deposited On:||04 Jun 2012 11:31|
|Last Modified:||13 Jun 2012 17:02|
|Supervisor(s):||Mahapatra, K K|
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