FPGA implementation of circular spatial filter under high noise variance conditions

Rajulapati , Bharat Kumar (2012) FPGA implementation of circular spatial filter under high noise variance conditions. MTech thesis.

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The noise in digital images is additive in nature in various cases. Such kind of noise is called to as Additive White Gaussian Noise (AWGN). This noise gets into image while transmission, reception, storage and retrieval It is difficult to suppress AWGN because it corrupts more or less all the pixels in a image. Some filters such mean filter had been proposed to suppress AWGN but in most cases it incorparates a blurring effect in the image. Image denoising is usually done before display or further processing like feature extraction, segmentation, object identification, texture analysis, etc. The intention of denoising is to suppress the noise efficiently and retaining the edges and other necessary features as far as possible.Many efficient digital image filters are found that perform well under low noise conditions. But in the cases of moderate and high noise conditions their performance is limited. Thus, it is felt that there is sufficient scope to investigate and develop quite efficient. And proposed a spatial filter named as circular spatial filter which performs well under high noise conditions. Suppose CSF has to be used for real time applications such as before displaying the video on HDTV a real time application. It is hard to implement this algorithm on a general purpose computer where high amount of concurrency is needed. So we have chosen FPGA as a target which is suitable for video and image processing. Here we chose virtex-5 Xilinx board to implement the algorithm. The performance of the designed filters is compared with the existing filters and the MATLAB simulation [1] in terms of peak-signal-to noise ratio, root-mean-squared error.

Item Type:Thesis (MTech)
Uncontrolled Keywords:FPGA,Image denoising,Circular spatial filter
Subjects:Engineering and Technology > Electronics and Communication Engineering > VLSI
Engineering and Technology > Electronics and Communication Engineering > Image Processing
Divisions: Engineering and Technology > Department of Electronics and Communication Engineering
ID Code:3965
Deposited By:bharat kumar rajulapati
Deposited On:12 Jun 2012 11:08
Last Modified:12 Jun 2012 11:08
Supervisor(s):Meher, S

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