Modeling & Performance Enhancement Analysis of Some Nanoscale MOSFET Structures

Abstract

Silicon-on-Insulator (SOI) has been the forerunner of the CMOS technology in the last few decades offering superior CMOS devices with higher speed, higher density and reduced second order effects for submicron VLSI applications. Recent experimental studies invigorated interest in Fully Depleted (FD) SOI devices because of their potentially superior scalability relative to bulk silicon CMOS devices. Various new structures with different engineering concepts have been reported to reduce the SCEs in SOI platform. Among them Strain engineering and high-k gate dielectric with metal gate technology are very popular for enhancing the carrier mobility and reduction of gate leakage current.
In this thesis, first physics based 2-D model for surface potential, threshold voltage and electric field for a Fully Depleted Strained Silicon on Insulator (FD-S-SOI) MOSFET by solving the two dimensional Poisson’s equation is presented. The model details the role of various MOS parameters like germanium concentration, body doping concentration, strained silicon thickness, oxide thickness and gate metal work function influencing the surface potential, threshold voltage and electric field. Then extensive numerical simulation is done to study the effect of device design engineering on the analog/RF performance of nanoscale DGMOSFET by varying the gate work function, channel length and gate oxide. Including the Short Channel Effects (SCEs) the important analog/RF figures of merit (FOMs) are also examined.
Finally one optimum device is presented with great immunization to SCEs and highly applicable to analog/RF applications.