Development of an fpga based image processing intellectual property core

Abstract

Traditional image processing algorithms are sequential in nature. When these algorithms are implemented in a real-time system, the response time will be high. In an embedded platform, such algorithms consumes more power because of more number of clock cycles required to execute the algorithm. With the advent of Field Programmable Gate Arrays (FPGA), massively parallel architectures can be developed to accelerate the execution speed of several image processing algorithms. In this work, such a parallel architecture is proposed to accelerate the SOBEL edge detection algorithm. To simulate this architecture, a model of video acquisition system is developed. This model will convert the incoming frames to digital composite video signals which can be processed by the edge detection architecture. An external software developed in Matlab will convert the frames in to hexadecimal format, and will feed the video acquisition model. The output of the edge detection processor will be a digital composite signal. A display module will convert the digital composite video signals in to hexadecimal format. Then with the help of an external Matlab program, the original image will be reconstructed. The result shown compares the sequential and parallel environments, and shows significant improvements in FPGA based implementations. The Modelsim simulation of SOBEL based edge detection algorithm for a 256 _ 256 frame, gave a result in 0.019 seconds for a clock speed of 10MHz, where as a Matlab based simulation took 0.22 seconds to finish this operation, which is a significant acceleration. Moreover, a new software simulation platform was developed as a part of this project, which will let the developer to give input as image and the output will be reproduced in the same format, while all the background processing will be carried out in VHDL