FPGA Implementation of Advanced Encryption Standard

Abstract

Security is a crucial parameter to be recognized with the improvement of electronic communication. Today most research in the field of electronic communication includes look into on security concern of communication. At present most by and large consumed and recognized standard for encryption of data is the Advanced Encryption Standard. AES was transformed to supplant the developing Data Encryption Standard. The AES calculation is fit for handling cryptographic keys which are of 256, 128, & 192 bits to encode & unscramble data in squares of 128 bits. The center of the calculation is made up of four key parts, which manage 8 bit data pieces. The whole 128 bit data to the calculation is dealt with into a 4 x 4 grid termed a state, to obtain the 8 bit square. Considering the complex nature of advance encryption standard (AES) algorithm, it requires a huge amount of hardware resources for its practical implementation. The extreme amount of hardware requirement makes its hardware implementation very burdensome. During this research, a FPGA scheme is introduced which is highly efficient in terms of resource utilization. In this scheme implementation of AES algorithm is done as a finite state machine (FSM). VHDL is used as a programming language for the purpose of design. Data path and control unit are designed for both cipher and decipher block, after that respective data path and control unit are integrated using structural modeling style of VHDL. Xilinx_ISE_14.2 software is being used for the purpose of simulating and optimizing the synthesizable VHDL code. The working of the implemented algorithm is tested using VHDL test bench wave form of Xilinx ISE simulator and resource utilization is also presented for a targeted Spartan3e XC3s500e FPGA.