VLSI implementation for security paradigm of AES including DPA attacks

Abstract

Cryptography is where security engineering meet mathematics. Modern cryptographic techniques have multiple applications, like access control, for electronic money transfers, for copyright protection as well as digitally sign documents. Since the usages are highly vital, users need to check the efficiency of the cryptographic techniques. Basically cryptography can be classified in two ways to make a stronger cipher— the stream cipher and the block cipher. In the former, one makes the encryption rule depend on a plaintext symbol’s position in the stream of plaintext symbols, while in the latter one encrypts several plaintext symbols at once in a block. Advanced Encryption Standard (AES) is a block symmetric cipher. With the exponential increase in processor’s speed, methods used to implement data security become more vital. Until the year 2000, Data Encryption Standard (DES) was the best cryptographic algorithm available. But with the advent of new technologies penetration through the secured walls was possible. High processor speeds assisted in vexing every possible key to break the best secured algorithm by that time. AES can be implemented in software, hardware, and firmware. The implementation can use table lookup process or routines that use a well-defined algebraic structure. AES 128 bit variant has been thoroughly analyzed using MATLAB. This core was designed with VHDL in a pipelined architecture and implemented in FPGAs whose results have been shown in this work.Throughseveral simulation results and researchesAES certainly proves to be more securedin comparison to other algorithmsone of the reasons being its larger key size. It is even defiant against Side Channel Attacks such as DPA.Numerous tests have failed to do statistical analysis of the ciphertext. In this work, to protect FPGAs from DPA attacksthe problem of randomized execution in a loop has been comparatively analysed. A few algorithms to randomize the implementation in a loop has been proposed. Algorithm RO, INRO and AINRO relate to the state where all task nodes in a DFG chargesimilarvolume of time in the execution. This AES 128 core is designed and developed for power analysis in ASIC implementation and the corresponding results are reported.