Design of Random Number Generator and Its Delay and Power Optimization

Abstract

A digital system is tested and diagnosed during its lifetime on numerous occasions. Test and diagnosis must be quick and have very high fault coverage. One way to ensure this is to specify test as one of the system functions, so it becomes self test. The system has several PCBs, each of which, in turn has multiple chips. The system controller can activate self-test simultaneously on all PCBs. These test result help to isolate faulty chips and boards. In this project Linear Feedback Shift Register (LFSR) method has been used to generate pseudo random tests. This method uses very little hardware and is currently the preferred built in self test pattern generation method. Mentor Graphics Design architect tool was used for designing of circuit. It was also used for measuring power and delay associated with the circuit for different technologies.