Modeling and Simulation of Non-Classical MOSFETs for HP and LSTP Applications at 20 nm Gate Length

Abstract

The endless miniaturization of Si-based Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) has the key for urging the electronic uprising. How-ever, scaling of the channel length is the enormous challenge to preserve the per-formance in terms of speed, power, and electrostatic integrity at each technologynodes. From the commencement of CMOS scaling, the simple planar MOSFETs are not up to the performance because of the increased SCEs and leakage cur-rent. To slacken the SCEs and leakage currents, different types of structures i.e.Multi-Gate MOSFETs like double-gate (DG), triple-gate (TG), FinFETs have in-troduced in the literature. Fully Depleted (FD) Silicon-On-Insulator (SOI) devices have shown potentially significant scalability when compared to bulk MOSFETs.In spite of, the introduced structures in literature are not offering concurrent SCE repression and improved circuit implementation. And some involve tangled processing not suggested for smooth integration into the here and now CMOS technology. The scaling capability of nanoscale ultra-thin (UT) silicon directly on insula-tor (SDOI) single gate (SG) and DG MOSFETs is investigated to overcome SCEs and improve power consumption. Dependence of underlap length on drain cur-rent, Subthreshold Slope (SS), transition frequency, delay, Energy Delay Product (EDP), etc. is studied for DG MOSFET and FinFET, to find the optimum value of underlap length for low power consumption. DG MOSFET is an excellent can-didate for high current drivability whereas FinFET provides better immunity toleakage currents and hence improved delay, EDP over DG MOSFET. Furthermore,FinFET provides a high value of transition frequency which indicates that it is faster than DG MOSFET. III-V channel materials are proposed for the discussed two structures to improve the On current at the same integration density as in Si-based channel FETs. The role of geometry parameters in sub 20 nm SOI Fin-FET is studied to find the optimum value of height and width of Fin for analogand RF circuit design. This work provides the influence of the height and width of Fin disparity on different performance matrices that comprises of static as well as dynamic figures of merit (FoMs). Based on the Aspect Ratio (WF in/HF in),the device can be divided into three parts, i.e., FinFET, Tri-gate, and PlanarMOSFET.CMOS for SG and DG is made using the combination of NMOS and PMOS by engineering the work function in order to have same threshold voltage for N-channel and P-channel MOS. The inverter is without doubt the core of all digital applications. Once its operation and characteristics are understood with clarity,designing more complicated structures such as NAND gates, multipliers, adders, and microprocessors are significantly explained. The performance of CMOS is articulated. All the dimensions are according to the ITRS 2013 datasheet. Thework provided here is requisited to give the purpose for forward experimental in-vestigation.