Panda, Nidhi (2016) Analysis of Edge Detection Technique for Hardware Realization. MTech thesis.
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Edge detection plays an important role in image processing and computer vision applications. Different edge detection technique with distinct criteria have been proposed in various literatures. Thus an evaluation of different edge detection techniques is essential to measure their effectiveness over a wide range of natural images with varying applications. Several performance indices for quantitative evaluation of edge detectors may be found in the literature among which Edge Mis-Match error (EMM), F-Measure (FM), Figure of Merit (FOM) and Precision and Recall (PR) curve are most effective. Several experiments on different database containing a wide range of natural and synthetic images illustrate the effectiveness of Canny edge detector over other detectors for varying conditions. Moreover, due to the ever increasing demand for high speed and time critical tasks in many image processing application, we have implemented an efficient hardware architecture for Canny edge detector in VHDL. The studied implementation technique adopts parallel architecture of Field Programmable Gate Array (FPGA) to accelerate the process of edge detection via. Canny’s algorithm. In this dissertation, we have simulated the considered architecture in Modelsim 10.4a student edition to demonstrate the potential of parallel processing for edge detection. This analysis and implementation may encourage and serve as a basis building block for several complex computer vision applications. With the advent of Field Programmable Gate Arrays (FPGA), massively parallel architectures can be developed to accelerate the execution speed of several image processing algorithms. In this work, such a parallel architecture is proposed to accelerate the Canny edge detection algorithm. The architecture is simulated in Modelsim 10.4a student edition platform.
|Item Type:||Thesis (MTech)|
|Uncontrolled Keywords:||Consensus Ground Truth,Edge Mismatch Error(EMM),FMeasure (FM),Figure of Merit(FOM),FPGA,Precision Recall(PR)curve, VHDL Architecture.|
|Subjects:||Engineering and Technology > Electrical Engineering > Image Segmentation|
Engineering and Technology > Electrical Engineering > Power Electronics
|Divisions:||Engineering and Technology > Department of Electrical Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||21 Sep 2017 12:39|
|Last Modified:||21 Sep 2017 12:39|
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