Katiyar, Jyotsna (2016) Atlas Based Simulation of Double Gate Tunnel Field Effect Transistor. BTech thesis.
With the advancement in technology various devices are designed with the complex structure of processors. In this simulation through the study of Double Gate Tunnel FET, device parameters are studied to meet the requirements of the technological developments. The scaling of large devices is done to fabricate more no. of devices on a single structure. The integration of large devices into small chip provides efficient advantages with a smaller area. But as the number of devices increases the amount of supply voltage required is high as well as the decreases in the area increases the device OFF- state current. To reduce all these problems TFET structure was designed to provide lower subthreshold swing. Several other structures like double gate tunnel FET is used to increase the ON-state current. The high- k and low-k dielectric were used with double gate. The high-k dielectric increases the channel capacitance and decreases the amount of subthreshold swing. Hence, the amount of supply voltage decreases and the power consumption is also reduced. Dual material gate structure was designed over hetro dielectric to provide better current since the gate material like silicon and poly silicon is used. It has been observed that the amount of current increases in the presence of light because the flow of carriers increases so, the effect was applied on double gate structure to get the desirable amount of current.
|Item Type:||Thesis (BTech)|
|Uncontrolled Keywords:||Scaling; Double Gate Tunnel FET; TFET; Channel capacitance|
|Subjects:||Engineering and Technology > Electronics and Communication Engineering > VLSI|
|Divisions:||Engineering and Technology > Department of Electronics and Communication Engineering|
|Deposited By:||Mr. Sanat Kumar Behera|
|Deposited On:||06 Dec 2016 21:38|
|Last Modified:||06 Dec 2016 21:38|
Repository Staff Only: item control page