Exploration of Novel Attributes of Hybrid FinFETs towards Analog/RF and Reliability Aspects

Abstract

MOSFETs with multiple gate structures, such as 3-D FinFETs have seen enormous interest for sub-22 nm applications. The n base devices are excellent in suppressing the short channel effects (SCEs) and have an immense control over the carriers in the channel. According to the International Technology Roadmap for Semiconductors (ITRS) prediction and previous literatures, the 3-D topologies are here to drive the commercial industries up to 5-nm technology node. The only innovations in lower technology nodes will be in the physical architecture or incorporation of new channel materials that are CMOS compatible. However, few challenges are still there for FinFETs to establish optimum ac and dc performances. Thus, a 3-D TCAD investigation of FinFETs is crucial to determine the best design options according to manufacturability without high-cost.
Hence in this thesis, we start with a unique attempt for detailed investigation of 3-D FinFET on dependency of process variability. The performances in view of analog and RF circuit applications through calibrated TCAD simulation are explored for the 3-D device architecture. The work is further extended for designing the emerging hybrid/Wavy FinFETs, i.e:, combination of ultra-thin-body (UTB), and 3-D FinFET on a single silicon-on-insulator (SOI) platform. Various attempts are made on the hybrid FinFETs to reduce certain limitations of nanoscale design and to provide a significant contribution in terms of improved performances of the miniaturized devices for the future technology nodes. In the subsequent chapters, further development of the proposed hybrid FinFETs is carried out. Moreover, the impact of various spacer technologies i.e:, symmetric and asymmetric single-k as well as dual-k, in the underlap region of hybrid FinFETs is systematically presented. The double material gate oxide (DMGO) concept i.e:, two different gate oxide materials (partially high-k and low-k), in symmetric dual-k spacer (SDS) hybrid FinFETs is also systematically analyzed with evaluating the zero temperature coe cient (ZTC) or temperature inflection point (TCP).
However, the primary challenge in the fin based devices are getting an ideal rectangular fin shape. Because of the non-ideal fabrication process steps in lithography, and etching result in a wider fin bottom as compared to the fin top. This leads to a non-rectangular shape of the fin channel. Such deviation in fin shape deteriorates the device performance with increasing SCEs, low on-off ratio, large subthreshold slope, and so on. Hence, the impact of fin shape from ideal fin angle (i.e:, Fin=900) to non-ideal n angle (i.e:, Fin=800) on a wide range performance matrix for the SDS hybrid FinFETs is well examined. Similarly, the variation of fin height (HFin) from 30 nm to 70 nm is further investigated. With the variation of HFin, and Fin in 3-D device simulation, the optimum configuration for the hybrid FinFETs is drawn in accordance to digital application perspective.
Finally, the reliability aspects became the primary bottleneck in further development of next generation technology. Advanced trends like use of new materials, sizing of the device, and structural innovations make the device more sensitive towards soft errors. These errors are random in nature (mainly because of external cosmic radiation) and not due to hardware related faults. It is necessary to investigate the impact of heavy ion irradiation in any kind of device from reliability aspect of the device for inclusion in circuit applications. In the last chapter consideration is given to the transient behavior of the proposed devices when they are subjected to heavy ion irradiation. With reference to the outcomes of this thesis work, further scope has been left for the researchers to design optimum and reliable device configurations to meet the demands of low standby power (LSTP) and/or high performance (HP) applications.