Junctionless Nanowire : Towards Logic Circuits and Memory Applications

Abstract

The increasing prominence of portable systems and the need to limit the power consumption (and hence heat dissipation) in very high density VLSI chips have led to rapid and innovative development of short channel multi-gate devices during the recent decades. The driving forces of these portable devices require low power consumption and must be good resilient to noise as they are being driven by very small voltages. These short channel devices need high electrostatic control over the channel which can be achieved by multiple-gate metal oxide semiconductors field effect transistors (MG-MOSFET). As we will go on scaling the devices the problem not only lies with the electrical characteristics but also with fabrication of the device. To avoid fabrication related issues and to achieve some improved performance junctionless devices are proposed.
In this dissertation, the short channel performance of the proposed Junctionless nanowire transistor (JNT) have been evaluated. As we know in integrated circuits (IC) transistors are the key components to evaluate its performance so, we have studied the performance of CMOS inverter and universal gates using the proposed device. To achieve significant performance proper current flow is required in pull up and down network, fro this sizing of both oppositely device is very important which has been covered in respective sections.
In modern chips most part (area) is mainly memory. As for memory design array of transistors connected in a sophisticated fashion is required so its very much important to analyze the performance. We have analyzed stability of static random access memory (SRAM) cell in terms of different noise margin criteria and its sizing constraints. For the first time in this work we have analyzed N-Curves for the proposed device.