Performance Study of Nano-Scale Transistor with
Conventional Transistor

Abstract

According to Moore‟s Law, the no of transistors in an IC chip doubles every 18 months. This leads in increase in power density. Hence in modern power circuits, the main factor of the circuit efficiency is power efficiency. Due to scaling, leakage power accounts for an increasingly large
portion of the total power consumption in deep submicron technologies. In this article, we proposed a methodology to find the problems occurring while scaling it into
small size with some factor. We have simulated the inverter circuit using CMOS in MATLAB, P-Spice (ICs used BSH107, BSH207) and nano-CMOS using T-Spice where we can vary the
physical dimensions of the MOSFET. The outputs were observed and the time delay was calculated. The above results showed that, as we go on reducing the size, the performance enhances. Due to some limitations, the CMOS were facing some of the problems like Draininduced
barrier lowering (DIBL), Velocity Saturation, Punch through, Oxide Breakdown, Channel length modulation.
Hence due to the above factors, FinFET technology has proposed as an alternative to deep submicron bulk CMOS. FinFET is likely to meet the performance requirements in the sub-20nm gate length regime. FinFET will replace the traditional MOSFET due to its better performance in
sub 20nm regime and also it has excellent control over the problems faced by the Traditional CMOS.